GitHub

SystemVerilog Clocking Blocks Tutorial

This repository is a hands-on tutorial for understanding and applying SystemVerilog clocking blocks and modports in a UVM-based testbench environment. It demonstrates how to: Synchronize ...
GitHub

Hardware-accelerated SHA-256 implemented on a PYNQ-Z2 FPGA. Includes custom SystemVerilog IP, AXI4-Lite/DMA integration, and Python/Jupyter interface. Achieves faster hashing ...

This repository contains the full implementation and documentation of a hardware-accelerated SHA-256 hashing engine developed as a final university project. The project leverages the Xilinx PYNQ-Z2 ...
IEEE

Development of a Verilog-Based System for Pattern Detection Using Convolutional Neural Networks

Abstract: Pattern detection is a foundational element in computer vision, crucial for advancements in autonomous driving, surveillance, and numerous other fields. Convolutional Neural Networks (CNNs) ...